R
UCF Location Constraints
UCF Location Constraints
Figure 12-3 provides the UCF constraints for the SPI serial Flash PROM, including the I/O
pin assignment and the I/O standard used.
# some connections shared with
SPI Flash,
DAC, ADC, and AMP
NET "SPI_MISO"
LOC = "AB20" |
IOSTANDARD
= LVCMOS33 ;
NET "SPI_MOSI"
NET "SPI_SCK"
NET "SPI_SS_B"
NET "ALT_SS_B"
LOC = "AB14" |
LOC = "AA20" |
LOC = "Y4" |
LOC = "Y5" |
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
= LVCMOS33 | SLEW
= LVCMOS33 | SLEW
= LVCMOS33 | SLEW
= LVCMOS33 | SLEW
=
=
=
=
SLOW
SLOW
SLOW
SLOW
|
|
|
|
DRIVE
DRIVE
DRIVE
DRIVE
=
=
=
=
8
8
8
8
;
;
;
;
# write-protect and reset controls for Atmel AT45DB161D PROM
NET "DATAFLASH_WP"
NET "DATAFLASH_RST"
LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
# write-protect control for ST M25P16 PROM
NET "ST_SPI_WP"
Figure 12-3:
LOC = "C13" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
UCF Location Constraints for SPI Flash Connections
Creating and Programming Configuration Images for SPI Serial
Flash
Refer to the “ Master SPI Mode ” chapter in the Spartan-3 Generation Configuration User Guide
for information on how to create and format FPGA configuration images for SPI serial
Flash and how to program SPI Flash using the Xilinx iMPACT software.
?
UG332: Spartan-3 Generation Configuration User Guide
SPI Flash PROM Programming Options
Starting with ISE ? 9.1i, Service Pack 2 and later, the iMPACT programming software
supports two different methods to program an attached SPI Flash PROM, as summarized
Using the Direct Programming Method , the programming cable communicates directly to
the SPI Flash PROM. The FPGA is not involved in the programming process and the FPGA
I/O pins that connect to the PROM must be in their high-impedance state (Hi-Z) during
programming. Hold the FPGA’s PROG_B input Low using jumper J16 to place the I/Os in
Hi-Z; the FPGA’s DONE pin remains Low.
Using the Indirect Programming Method , the programming cable connects to the FPGA’s
JTAG port. The iMPACT software first programs the FPGA with a special design that
performs the SPI PROM programming and uses the JTAG interface as a serial
communications port. During the process, the FPGA’s DONE output is High and the
DONE LED is lit because the FPGA is configured with the programming logic. All pins
that are not connected to the SPI Flash PROM or the JTAG interface have an internal
pull-up resistor to the V CCO voltage supply associated with the pin.
Spartan-3A/3AN FPGA Starter Kit Board User Guide www.xilinx.com
UG334 (v1.1) June 19, 2008
95
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